This invention relates to CMOS FET devices; and more particularly to methods of manufacture of FET devices, in which offset spacers are formed prior to the steps of formation of source/drain extensions followed by formation of sidewall spacers and devices manufactured thereby.
In the process of manufacture of CMOS (Complementary Metal Oxide Semiconductor) FET (Field Effect Transistor) devices (hereinafter referred to as MOSFET devices), during an intermediate point in the process gate electrode stacks of gate dielectric below and polysilicon above are formed on the top surface of a doped semiconductor substrate. Below each of the MOSFET devices, a channel will be located directly below the gate electrode in the semiconductor substrate. Subsequently, offset spacers composed of a dielectric material, e.g. silicon oxide, are formed on the vertical sidewalls of the gate electrode stacks to protect the channel below the gate electrode stack from introduction of counterdopant therein during the subsequent step of formation of source/drain extensions. Next, the source/drain extensions are formed by counterdoping regions in the surface of the semiconductor substrate with a light implantation of dopant aside from the gate electrode stacks. Then sidewall spacers composed of a material, e.g. silicon nitride, are formed on the sidewalls of the offset spacers to provide further spacing away from the channel of the source/drain regions which will be formed thereafter.
Forming an offset spacer is conventionally done by depositing and/or growing a uniform layer of silicon oxide on the sidewalls of a gate electrode stack followed by performing an anisotropic etch to leave silicon oxide offset spacers only on the gate electrode sidewalls (i.e. remove silicon oxide from the exposed horizontal surfaces including the top surfaces of the semiconductor substrate). This approach suffers from too much process variation due to the problem of excessive recessing of the crystalline silicon surface from the RIE over-etching of MOSFET devices as shown by FIGS. 3A and 3B.
FIGS. 3A and 3B are TEM images of a prior art MOSFET structure 8 in an early stage in a prior art process of manufacture thereof.
FIG. 3A is a low magnification TEM image with a 20.00 nm scale. The MOSFET structure 8 includes a silicon substrate 11 on which a gate electrode stack 23 is formed. The gate electrode stack 23 comprises a polysilicon gate electrode 20 formed over a gate dielectric layer 12 composed of silicon oxide formed over the surface of the silicon substrate 11 above a region to be formed as the channel region CH of a MOSFET device in the substrate 11. The gate electrode polysilicon 20 has a length of 46.1 nm. The sidewalls of the gate electrode 20 are covered with a pair of offset spacers 24 (35 Å thick) which were formed by deposition of a layer of silicon dioxide onto the surface of the device 8. Then the silicon dioxide was shaped by RIE processing into those offset spacers 24 shown on those sidewalls of the gate electrode 20. There is a RIE residual film 42 on the surface of the silicon substrate 11. A recess 40 in the top surface of the silicon substrate 11 is shown on either side of the channel CH. There is a problem that unwanted recesses 40 have been formed in the surface of the silicon substrate 11 indicated by the indicia 40 on either side of the gate electrode stack 23 and the channel CH. The unwanted recesses 40 (which have a depth 43 of about 49 Å) were formed due to the RIE processing used to shape the offset spacer 24 by etching it back. Unfortunately, the surface of the silicon semiconductor substrate 11 was etched excessively, as well. The depth 43 of 49 Å of the recesses 40 in the silicon substrate 11 has been found to be excessive which has caused a problem with overlap capacitance (Cov) and degradation of device performance in the devices of the scale currently being manufactured.
FIG. 3B shows the MOSFET structure 8 of FIG. 3A (a high magnification TEM image marked with a 7.00 nm scale.) The silicon substrate 11 supports the gate electrode stack 23 including the polysilicon gate electrode 20 formed over the gate dielectric layer 12 with the offset spacer 24 (35 Å thick) and RIE residual film 42 on the surface of the silicon substrate 11. The recess 40 in the surface of the silicon substrate 11 due to the RIE process used to shape the offset spacers 24 is also seen. At the bottom, the offset spacer thickness is indicated to be 29 Å and the thickness is 35 Å at a point located thereabove. The silicon recess 40 is indicated to have a depth of about 49 Å. The residual film 42 is shown to have a thickness of about 26 Å. The thickness of the gate oxide layer is indicated to be about 36 Å.
The device overlap capacitance Cov is very sensitive and varies as a function of the depth of the recess 40 in the surface of the silicon substrate 11 at the edges of the gate electrode stack 23. The degree of variation in the Cov has been a key technology challenge for the past several generations of shrinkage in the scale of MOSFET devices and is becoming more serious as device features scale to smaller and smaller dimensions. Moreover, this level of recess may cause undesired degradation of device performance.
U.S. Pat. No. 6,037,639 of Ahmad entitled “Fabrication of Integrated Devices Using Nitrogen Implantation” describes a process wherein nitrogen is implanted into the substrate of CMOS devices, which is employed to form a silicon nitride plug at the edge of the gate oxide of a MOSFET device to reduce the electric field in this region in order to suppress hot electron degradation. A step of nitrogen implantation comprising amorphization is performed in which regions of nitrogen ion implanted areas are formed in the substrate, altering the ordered substrate crystal structure and distorting the crystal lattice to accommodate these extra atoms in the implantation area. The amount of the nitrogen doping may range from about 1×1012 atoms to 1×1015 atoms at a very high implantation energy is in the range of about 10 keV to 100 keV. Following the step of nitrogen implantation, a thermal spacer growth step is caffied out to form a surface silicon oxide layer over the future locations of source/drain regions and on the sidewalls of transistor gates. While this step forms a vertical sidewall insulating spacer on the sides of the polysilicon gate, it also repairs the implantation damage in the nitrogen implanted areas and produces a slight bird's beak structure under both the lower edges of each transistor polysilicon gate. Due to its shape, this structure is called a Gate Bird's Beak (GBB,) which increases the thickness of the gate oxide at the lower edges of the gate polysilicon in order to relieve the electric field intensity at the edges or corners of the gate structure. The spacer growth comprises a thermal oxidation forming a spacer composed of oxide. Preferred parameters for the oxidation comprise heating the structure to between about 700° C. and 1,100° C., more preferably between about 850° C. and 950° C. and most preferably about 907° C. The length of the oxidation may range from about 5 minutes to about an hour, more preferably between about 10 minutes and 20 minutes, and most preferably about 15 minutes. A dry oxygen atmosphere is preferred. Alternatively, the spacer growth may comprise a nitridation step. In Ahmad, the spacer growth step is a heating step, like a conventional post-doping thermal drive step. The oxidation of the substrate causes upward migration and consumption of silicon atoms from the nitrogen implanted areas (as well as from the gate polysilicon), to form an oxide layer on the surface of the semiconductor, above the nitrogen implanted areas as the result of upward motion of the implanted nitrogen atoms. The nitrogen concentration difference between the growing oxide layer and the nitrogen implanted areas provides the driving force for the reaction. The implanted nitrogen atoms migrate to the growing oxide layer at the substrate surface and a silicon nitride layer is formed between the growing oxide layer and the surface of the substrate. As well known in the art, silicon nitride has a high dielectric constant, higher in particular than silicon oxide, and is an effective barrier or protective layer against hot carrier injection at the gate edges, which is otherwise induced by the high electric field present in a ULSI device. Significantly, the silicon nitride layer also extends laterally at least partially under the gate polysilicon in the region of the GBB, due to mobility of atoms during the oxidation, and to form a nitride edge portion at least partially underlying the gate corner. The nitride edge portion may form only the oxide/substrate interface, as illustrated, or nitrogen atoms may diffuse through the growing oxide to the gate polysilicon. This laterally nitride grown edge portion effectively isolates the lower polysilicon gate edges from the neighboring source/drain regions and thus effectively minimizes the high electric field induced current leakages into the gate poly 112. As previously mentioned, in prior art applications the conventional oxide spacer deposition and the following heat treatment tend to limit the nitride formation to the region under the deposited sidewall spacer.
U.S. Pat. No. 6,229,198 of Ibok et al. entitled “Non-Uniform Gate Doping for Reduced Overlap Capacitance” describes a transistor comprising a gate electrode with a non-uniform impurity profile increasing from the drain side to the source side, thereby reducing the overlap capacitance between the gate electrode and drain region. In addition, the transverse electrical field in the channel region is maintained by evenly disposing gate impurity atoms throughout the entire gate electrode.
U.S. Pat. No. 6,297,106 of Pan et al. entitled “Transistors with Low Overlap Capacitance” describes the fabrication of integrated circuit devices and a method for reducing gate to drain and gate to source overlap capacitance of deep sub-micron CMOS devices to reduce device switching times by customizing the gate insulating layer, such that the dielectric constant, K, is lower in the gate to drain and gate to source overlap regions, relative to the more centrally located gate region between the source and drain.
U.S. Pat. No. 6,720,213 Gambino et al. for “Low-K Gate Spacers By Fluorine Implantation” describes a MOSFET device and a method of fabricating a MOSFET device having low-K dielectric oxide gate sidewall spacers produced by fluorine implantation, by implanting fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.
U.S. Pat. No. 6,838,777 of Igarashi entitled “Semiconductor Device and Method of Manufacturing the Same” describes gate electrodes formed on a semiconductor substrate, each with a gate insulating film interposed therebetween. Offset spacers are formed on opposite faces of each of the gate insulating film and the gate electrodes. Diffusion layers are formed in the semiconductor substrate on opposite sides of a portion of the semiconductor substrate immediately under each of the gate electrodes by ion implantation. The gate electrodes have various configurations, e.g. a gate electrode having a rectangular section, an upwardly tapered gate electrode, and a downwardly tapered gate electrode. Making Field Effect Transistors Having Self-Aligned Source and Drain Regions Using
U.S. patent application Ser. No. 2005/0145942 of Rainer E Gehres entitled “Method of Independently Controlled Spacer Widths” describes a method for defining spacings between the gates of FETs of an integrated circuit and the source/drain regions thereof. The spacings differ in width between a first FET and a second FET. The method includes forming gate stacks of the integrated circuit over a substrate, and forming first spacers on gate stack sidewalls. Then second spacers are formed over the first spacers. Next, source/drain regions of the first FET are formed in alignment with the second spacers of a first gate stack of the gate stacks. Next the second spacers are removed from the first spacers of the gate stacks. Then the first spacers of a second gate stack are etched anisotropically substantially vertically to remove horizontally extending portions of the first spacers, and source and drain regions of the second FET are formed in alignment with portions of the first spacers of the first gate stack remaining after the etching.